1. Field of the Invention
The present invention relates generally to semiconductor manufacturing process, and more specifically, to a method using a hard mask on the metal gate to form contacts structure simultaneously during a plurality of etching processes.
2. Description of the Prior Art
Along with the continuous miniaturization of the Integrated Circuits (IC), the line width of interconnections and the feature size of semiconductor devices have continuously shrunk. In general, discrete devices in integrated circuits are connected to each other through contact plugs (or contact slots) and interconnection structures, and their related fabrication methods have become an important matter in the next-generation semiconductor devices.
In current fabricating processes, due to the limitations of the back end of the line (BEOL) process capacity, the yield of contact plugs with high aspect ratio (HAR) is relatively low and cannot reach the new requirements. In order to overcome this drawback, a double patterning technique, generally including two photolithographic and two etching processes (2P2E) has been invented in order to fabricate required device patterns. Generally, a contact is divided into two parts, a lower contact structure and an upper contact structure (i.e. the metal level zero, M0). After the lower contact structure is formed completely, the M0 is continuously formed. The M0 can be a pole structure or a slot structure. However, since the upper contact structure (M0) and the lower contact structure are formed in different steps, a barrier layer will exist between the upper contact structure (M0) and the lower contact structure, thereby affecting the conductivity of the contact. Besides, the manufacturing process is too complex.
Accordingly, in order to overcome the above-mentioned drawbacks, there is a need to provide a modified method for fabricating interconnection structures with better yields.